1. Field of the Invention
The present invention relates to a technique of testing a semiconductor memory with built-in security features.
2. Description of the Background Art
In some semiconductor memories such as mask ROMs or some non-volatile memories, contents are stored in advance at the time of manufacture according to a user's order. A semiconductor memory of this type (hereinafter referred to as “semiconductor memory for content storage”) may be given various security features to avoid unauthorized reading of stored contents.
Typical security features include descrambling of a received address signal at an exclusive OR circuit using predetermined key information, scrambling of a data signal to be output at an exclusive OR circuit using predetermined key information, and the like.
When a semiconductor memory for content storage equipped with these security features is tested before shipment, a memory is ideally subjected to reading in its entirety with security features activated to perform a total function test. However, such a complicated operational test through a conventional memory-specific tester requires considerably high test cost. Thus in general, a test targeted for a memory core alone (memory-core-only-test) and a test covering security features and a memory core (total function test) are independently performed.
The memory-core-only-test is equivalent to a test that has been performed on a conventional semiconductor memory with no security feature, and is intended to read a memory in its entirety. The memory-core-only-test should not be omitted in terms of reliability of a semiconductor memory. Such a test is a specialty of a memory-specific tester, and does not put pressure on test cost.
The total function test is not targeted for a conventional semiconductor memory with no security feature. Improvement in efficiency of the total function test is an important issue to realize reduction of the total cost of a semiconductor memory for content storage equipped with security features.
With reference to FIG. 6, a semiconductor memory 110 for content storage receives an address A0 from outside, and outputs data D0 corresponding to the address A0 from a memory core 113. An address bus and a data bus may be physically different. Alternatively, an address input cycle and a data output cycle may time-share a common bus.
FIG. 7 shows an example of a semiconductor memory for content storage with built-in security features. A semiconductor memory 110 for content storage has a security circuit 111 that includes a descrambling circuit 111a and a scrambling circuit 111b. 
The descrambling circuit 111a receives a scrambled address A1, descrambles the address A1 using address key information Ka, and outputs a descrambled address A0 to the memory core 113. The memory core 113 outputs data D0 corresponding to the address A0.
The scrambling circuit 111b scrambles the data D0 using data key information Kd, and outputs scrambled data D1. The data D1 is sent to the outside of the semiconductor memory 110 for content storage.
In order to facilitate test before shipment, some semiconductor memories for content storage with built-in security features are provided with a path for bypassing a security circuit as shown in FIG. 8. This allows implementation of the memory-core-only-test. That is, in the implementation of the memory-core-only-test, the address A0 bypasses the security circuit 111 to be sent to the memory core 113 as shown by a solid line of FIG. 8. The data D0 read from the memory core 113 bypasses the security circuit 111 to be sent to the outside of the semiconductor memory 110 for content storage as also shown by a solid line of FIG. 8.
FIG. 9 shows how the memory-core-only-test is implemented using a memory-specific tester 130. The memory-specific tester 130 causes an address generation circuit 131 to automatically generate and output the address A0 to the semiconductor memory 110. The address A0 sequentially designates addresses from a start address to an end address.
In the implementation of the memory-core-only-test, the semiconductor memory 110 for content storage is controlled to bypass the security circuit 111 and data is read from the memory core 113. The data D0 given from the semiconductor memory 110 for content storage and output expectation data stored in a buffer 135 are sequentially compared in an expectation comparison circuit 133 to implement the memory-core-only test.
In the implementation of the memory-core-only-test, the data stored in the memory core 113 and the output expectation data stored in the buffer 135 are the same. The output expectation data should be replaced according to contents.
FIG. 10 shows how the total function test is implemented using the memory-specific tester 130. In the implementation of the total function test, the scrambled address A1 should be given to the semiconductor memory 100 for content storage. The memory-specific tester 130 cannot be operative to automatically generate the scrambled address.
Thus the scrambled address A1 should be stored in advance as input pattern data in the buffer 135. The memory-specific tester 130 sequentially reads the input pattern data from the buffer 135 and sends the read data as the scrambled address A1 to the semiconductor memory 110 for content storage.
In the semiconductor memory 110 for content storage, the descrambling circuit 111a descrambles the address A1 using the address key information Ka to generate the address A0. The address A0 is supplied to the memory core 113 and then the data D0 is read from the memory core 113. The data D0 is thereafter subjected to scrambling using the data key information Kd at the scrambling circuit 111b. The scrambled data D1 is given from the semiconductor memory 110 for content storage. In the memory-specific tester 130, the received data D1 and the output expectation data stored in the buffer 135 are sequentially compared at the expectation comparison circuit 133 to implement the total function test.
The memory-core-only-test and the total function test are implemented in the manner described above. Thus a semiconductor memory for content storage equipped with security features can be tested before shipment.
The above-described total function test suffers from a problem that a combination of the input pattern data and the output expectation data (hereinafter also referred to as “test pattern”) stored in a buffer should be changed according to the contents stored in a semiconductor memory.
The output expectation data stored in a buffer should also be changed in the memory-core-only-test according to the contents in a memory. However, in order to ensure reliability of a memory, the memory-core-only test should not be omitted.
When a semiconductor memory for content storage equipped with security features is subjected to the memory-core-only-test and the total function test, a test pattern responsive to each test should be prepared, resulting in test cost increase.
If a memory tester has a large-sized buffer, a test pattern for the total function test and a test pattern for the memory-core-only-test can be separately stored in respective regions. In this case, both test patterns can be replaced at once in response to the change of the type of a semiconductor memory to be subjected to the tests. However, due to limitations on the capacity of a buffer, both test patterns cannot be stored in the same buffer in many cases. Thus in general, a test pattern is replaced by the following option (1) or (2):
(1) to replace a test pattern several times using one memory tester; or
(2) to use a plurality of memory testers.
In either case, each output expectation data for use in the total function test and in the memory-core-only-test should be replaced respectively according to contents. This causes a heavy burden of generating test patterns, and such a burden is desirably reduced.
The option (2) requires reduced number of replacement operations of a test pattern as compared to the option (1). Thus the option (2) is expected to significantly reduce test cost, as long as a burden of generating test patterns for use in the total function test is reduced.
In order to tighten security, the key information Ka and Kd given to the security circuit 111 may be varied according to the contents stored in the memory core 113. In this case, in addition to the output expectation data, the input pattern data should also be changed according to the contents stored in the memory core 113. This causes a heavier burden of generating test patterns and requires complicated works of replacement of a test pattern.